Allwinner /D1H /SMHC[0] /SMHC_CTRL

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Interpret as SMHC_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (no_effect)SOFT_RST 0 (no_effect)FIFO_RST 0 (DMA_RST)DMA_RST 0 (disable)INE_ENB 0 (disable)DMA_ENB 0 (disable)CD_DBC_ENB 0 (SDR)DDR_MOD_SEL 0 (C1)TIME_UNIT_DAT 0 (C1)TIME_UNIT_CMD 0 (DMA)FIFO_AC_MOD

INE_ENB=disable, FIFO_AC_MOD=DMA, DMA_ENB=disable, SOFT_RST=no_effect, DDR_MOD_SEL=SDR, TIME_UNIT_DAT=C1, TIME_UNIT_CMD=C1, CD_DBC_ENB=disable, FIFO_RST=no_effect

Description

Control Register

Fields

SOFT_RST

Software Reset

0 (no_effect): undefined

1 (reset): undefined

FIFO_RST

FIFO Reset

0 (no_effect): undefined

1 (reset): undefined

DMA_RST

DMA Reset

INE_ENB

GLobal Interrupt Enable

0 (disable): Disable interrupts

1 (enable): Enable interrupts

DMA_ENB

DMA Global Enable

0 (disable): Disable DMA to transfer data via AHB bus

1 (enable): Enable DMA to transfer data

CD_DBC_ENB

Card Detect (Data[3] status) De-bounce Enable

0 (disable): Disable de-bounce

1 (enable): Enable de-bounce

DDR_MOD_SEL

DDR Mode Select

0 (SDR): SDR mode

1 (DDR): DDR mode

TIME_UNIT_DAT

Time unit for data line

0 (C1): 1 card clock period

1 (C256): 256 card clock period

TIME_UNIT_CMD

Time unit for command line

0 (C1): 1 card clock period

1 (C256): 256 card clock period

FIFO_AC_MOD

FIFO Accesss Mode

0 (DMA): DMA bus

1 (AHB): AHB bus

Links

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